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Update Nax/Vexii

This commit is contained in:
Dolu1990 2024-07-12 16:17:30 +02:00
parent 22ff3ac42d
commit 9fa1b4c123
2 changed files with 3 additions and 4 deletions
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3
litex/soc/cores/cpu/naxriscv/core.py
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@ -320,9 +320,8 @@ class NaxRiscv(CPU):
def generate_netlist(reset_address):
vdir = get_data_mod("cpu", "naxriscv").data_location
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "43195dd1", NaxRiscv.update_repo)
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "ba63ee6d", NaxRiscv.update_repo)
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")

4
litex/soc/cores/cpu/vexiiriscv/core.py
View File

@ -156,7 +156,7 @@ class VexiiRiscv(CPU):
VexiiRiscv.vexii_args += " --with-mul --with-div --allow-bypass-from=0 --performance-counters=0"
VexiiRiscv.vexii_args += " --fetch-l1 --fetch-l1-ways=2"
VexiiRiscv.vexii_args += " --lsu-l1 --lsu-l1-ways=2 --with-lsu-bypass"
VexiiRiscv.vexii_args += " --relaxed-branch --relaxed-btb"
VexiiRiscv.vexii_args += " --relaxed-branch"
if args.cpu_variant in ["linux", "debian"]:
VexiiRiscv.vexii_args += " --with-rva --with-supervisor"
@ -164,7 +164,7 @@ class VexiiRiscv(CPU):
VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64"
if args.cpu_variant in ["debian"]:
VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy"
VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy --fpu-ignore-subnormal"
if args.cpu_variant in ["linux", "debian"]:
VexiiRiscv.vexii_args += " --with-btb --with-ras --with-gshare"