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vexriscv: Fix some floating signals 

Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-05-04 17:27:21 +01:00
parent fcd518b5d0
commit a048ba47c4
1 changed files with 3 additions and 0 deletions
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3
litex/soc/cores/cpu/vexriscv/core.py
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@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR):
i_dBusWishbone_ERR=dbus.err) i_dBusWishbone_ERR=dbus.err)
if "linux" in variant: if "linux" in variant:
# Tie zero to prevent 1'bx here
self.cpu_params["i_softwareInterrupt"] = 0
self.cpu_params["i_externalInterruptS"] = 0
self.add_timer() self.add_timer()
if "debug" in variant: if "debug" in variant: