vexriscv: Fix some floating signals

Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:27:21 +01:00 · 2019-05-04 17:27:21 +01:00 · a048ba47c4
parent fcd518b5d0
commit a048ba47c4
1 changed files with 3 additions and 0 deletions
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR):
                i_dBusWishbone_ERR=dbus.err)

        if "linux" in variant:
+            # Tie zero to prevent 1'bx here
+            self.cpu_params["i_softwareInterrupt"] = 0
+            self.cpu_params["i_externalInterruptS"] = 0
            self.add_timer()

        if "debug" in variant: