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litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk only apply constraints on eth_rx_clk

This commit is contained in:
Gwenhael Goavec-Merou 2023-08-31 11:36:24 +02:00
parent 9854c9f322
commit a071cc343d
1 changed files with 10 additions and 4 deletions
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6
litex/soc/integration/soc.py
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@ -1702,8 +1702,11 @@ class LiteXSoC(SoC):
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
if not eth_rx_clk is eth_tx_clk:
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
else:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
# Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
@ -1761,8 +1764,11 @@ class LiteXSoC(SoC):
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
if not eth_rx_clk is eth_tx_clk:
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
else:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
# Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):