Merge pull request #564 from shenki/microwatt-updates

Microwatt updates

litex/soc/cores/cpu/microwatt/boot-helper.S

@@ -1,4 +1,7 @@
 .section    .text, "ax", @progbits
 .global     boot_helper
+// void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr)
 boot_helper:
-	nop # FIXME
+	mtctr 	%r6,
+	bctrl
+	ba	0

litex/soc/cores/cpu/microwatt/core.py

@@ -151,6 +151,9 @@ class Microwatt(CPU):
             # Writeback
             "writeback.vhdl",
 
+            # MMU
+            "mmu.vhdl",
+
             # Core
             "core_debug.vhdl",
             "core.vhdl",

litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl

@@ -59,7 +59,7 @@ architecture rtl of microwatt_wrapper is
     signal wishbone_data_in  : wishbone_slave_out;
     signal wishbone_data_out : wishbone_master_out;
 
-    signal xics_in : XicsToExecute1Type;
+    signal core_ext_irq 	     : std_ulogic;
 
 begin
 
@@ -87,8 +87,8 @@ begin
     wishbone_data_sel      <= wishbone_data_out.sel;
     wishbone_data_we       <= wishbone_data_out.we;
 
-    -- xics_in mapping
-    xics_in.irq <= '0';
+    -- core_ext_irq mapping
+    core_ext_irq <= '0';
 
     microwatt_core : entity work.core
         generic map (
@@ -114,7 +114,7 @@ begin
             dmi_wr            => dmi_wr,
             dmi_ack           => dmi_ack,
 
-            xics_in           => xics_in,
+            ext_irq           => core_ext_irq,
 
             terminated_out    => terminated_out
         );

litex/soc/cores/cpu/microwatt/system.h

@@ -5,8 +5,11 @@
 extern "C" {
 #endif
 
-__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
-__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
+static inline void flush_cpu_icache(void)
+{
+	__asm__ volatile ("icbi 0,0; isync" : : : "memory");
+}
+static inline void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);