Merge pull request #564 from shenki/microwatt-updates
Microwatt updates
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commit
a086237a07
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@ -1,4 +1,7 @@
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.section .text, "ax", @progbits
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.section .text, "ax", @progbits
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.global boot_helper
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.global boot_helper
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// void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr)
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boot_helper:
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boot_helper:
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nop # FIXME
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mtctr %r6,
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bctrl
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ba 0
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@ -151,6 +151,9 @@ class Microwatt(CPU):
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# Writeback
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# Writeback
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"writeback.vhdl",
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"writeback.vhdl",
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# MMU
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"mmu.vhdl",
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# Core
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# Core
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"core_debug.vhdl",
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"core_debug.vhdl",
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"core.vhdl",
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"core.vhdl",
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@ -59,7 +59,7 @@ architecture rtl of microwatt_wrapper is
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signal wishbone_data_in : wishbone_slave_out;
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signal wishbone_data_in : wishbone_slave_out;
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signal wishbone_data_out : wishbone_master_out;
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signal wishbone_data_out : wishbone_master_out;
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signal xics_in : XicsToExecute1Type;
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signal core_ext_irq : std_ulogic;
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begin
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begin
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@ -87,8 +87,8 @@ begin
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wishbone_data_sel <= wishbone_data_out.sel;
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wishbone_data_sel <= wishbone_data_out.sel;
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wishbone_data_we <= wishbone_data_out.we;
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wishbone_data_we <= wishbone_data_out.we;
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-- xics_in mapping
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-- core_ext_irq mapping
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xics_in.irq <= '0';
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core_ext_irq <= '0';
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microwatt_core : entity work.core
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microwatt_core : entity work.core
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generic map (
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generic map (
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@ -114,7 +114,7 @@ begin
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dmi_wr => dmi_wr,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_ack,
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dmi_ack => dmi_ack,
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xics_in => xics_in,
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ext_irq => core_ext_irq,
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terminated_out => terminated_out
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terminated_out => terminated_out
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);
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);
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@ -5,8 +5,11 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
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static inline void flush_cpu_icache(void)
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
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{
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__asm__ volatile ("icbi 0,0; isync" : : : "memory");
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}
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static inline void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
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void flush_l2_cache(void);
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait(unsigned int ms);
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