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host: add support for various csr_data width (8 & 32 tested, but should work with others)

This commit is contained in:
Florent Kermarrec 2014-06-26 11:09:59 +02:00
parent 0f9bc5ad6e
commit a0df5baa55
2 changed files with 8 additions and 7 deletions
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11
miscope/host/regs.py
View File

@ -1,11 +1,12 @@
import csv
class MappedReg:
def __init__(self, readfn, writefn, name, addr, length, mode):
def __init__(self, readfn, writefn, name, addr, length, busword, mode):
self.readfn = readfn
self.writefn = writefn
self.addr = addr
self.length = length
self.busword = busword
self.mode = mode
def read(self):
@ -15,14 +16,14 @@ class MappedReg:
for i in range(self.length):
r |= self.readfn(self.addr + 4*i)
if i != (self.length-1):
r <<= 8
r <<= self.busword
return r
def write(self, value):
if self.mode not in ["rw", "wo"]:
raise KeyError(name + "register not writable")
for i in range(self.length):
dat = (value >> ((self.length-1-i)*8)) & 0xff
dat = (value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1)
self.writefn(self.addr + 4*i, dat)
class MappedRegs:
@ -37,12 +38,12 @@ class MappedRegs:
raise KeyError("No such register " + attr)
def build_map(addrmap, readfn, writefn):
def build_map(addrmap, busword, readfn, writefn):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
name, addr, length, mode = item
addr = int(addr.replace("0x", ""), 16)
length = int(length)
d[name] = MappedReg(readfn, writefn, name, addr, length, mode)
d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
return MappedRegs(d)

4
miscope/host/uart2wishbone.py
View File

@ -10,12 +10,12 @@ def write_b(uart, data):
class Uart2Wishbone:
WRITE_CMD = 0x01
READ_CMD = 0x02
def __init__(self, port, baudrate=115200, addrmap=None, debug=False):
def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
self.port = port
self.baudrate = str(baudrate)
self.debug = debug
self.uart = serial.Serial(port, baudrate, timeout=0.25)
self.regs = build_map(addrmap, self.read, self.write)
self.regs = build_map(addrmap, busword, self.read, self.write)
def open(self):
self.uart.flushOutput()