fhdl/verilog: Give more explict names to print functions.
This commit is contained in:
Florent Kermarrec
parent
86178ed2d9
commit
a18107f795
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@ -82,9 +82,9 @@ _ieee_1800_2017_verilog_reserved_keywords = {
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"wor", "xnor", "xor",
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}
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# Print Signals ------------------------------------------------------------------------------------
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# Print Signal -------------------------------------------------------------------------------------
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def _printsig(ns, s):
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def _print_signal(ns, s):
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if s.signed:
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n = "signed "
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else:
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@ -94,25 +94,25 @@ def _printsig(ns, s):
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n += ns.get_name(s)
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return n
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# Print Constants ----------------------------------------------------------------------------------
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# Print Constant -----------------------------------------------------------------------------------
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def _printconstant(node):
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def _print_constant(node):
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if node.signed:
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sign = "-" if node.value < 0 else ""
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return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True)
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else:
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return str(node.nbits) + "'d" + str(node.value), False
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# Print Expressions --------------------------------------------------------------------------------
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# Print Expression ---------------------------------------------------------------------------------
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def _printexpr(ns, node):
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def _print_expression(ns, node):
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if isinstance(node, Constant):
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return _printconstant(node)
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return _print_constant(node)
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elif isinstance(node, Signal):
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return ns.get_name(node), node.signed
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elif isinstance(node, _Operator):
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arity = len(node.operands)
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r1, s1 = _printexpr(ns, node.operands[0])
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r1, s1 = _print_expression(ns, node.operands[0])
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if arity == 1:
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if node.op == "-":
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if s1:
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@ -124,7 +124,7 @@ def _printexpr(ns, node):
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r = node.op + r1
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s = s1
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elif arity == 2:
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r2, s2 = _printexpr(ns, node.operands[1])
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r2, s2 = _print_expression(ns, node.operands[1])
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if node.op not in ["<<<", ">>>"]:
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if s2 and not s1:
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r1 = "$signed({1'd0, " + r1 + "})"
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@ -134,8 +134,8 @@ def _printexpr(ns, node):
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s = s1 or s2
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elif arity == 3:
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assert node.op == "m"
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r2, s2 = _printexpr(ns, node.operands[1])
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r3, s3 = _printexpr(ns, node.operands[2])
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r2, s2 = _print_expression(ns, node.operands[1])
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r3, s3 = _print_expression(ns, node.operands[2])
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if s2 and not s3:
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r3 = "$signed({1'd0, " + r3 + "})"
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if s3 and not s2:
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@ -150,29 +150,28 @@ def _printexpr(ns, node):
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if isinstance(node.value, Signal) \
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and len(node.value) == 1 \
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and node.start == 0 and node.stop == 1:
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return _printexpr(ns, node.value)
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return _print_expression(ns, node.value)
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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r, s = _printexpr(ns, node.value)
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r, s = _print_expression(ns, node.value)
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return r + sr, s
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elif isinstance(node, Cat):
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l = [_printexpr(ns, v)[0] for v in reversed(node.l)]
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l = [_print_expression(ns, v)[0] for v in reversed(node.l)]
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return "{" + ", ".join(l) + "}", False
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elif isinstance(node, Replicate):
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return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
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return "{" + str(node.n) + "{" + _print_expression(ns, node.v)[0] + "}}", False
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else:
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raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
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# Print Nodes --------------------------------------------------------------------------------------
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# Print Node ---------------------------------------------------------------------------------------
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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def _printnode(ns, at, level, node, target_filter=None):
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def _print_node(ns, at, level, node, target_filter=None):
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if target_filter is not None and target_filter not in list_targets(node):
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return ""
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elif isinstance(node, _Assign):
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@ -184,29 +183,29 @@ def _printnode(ns, at, level, node, target_filter=None):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
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return "\t"*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n"
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elif isinstance(node, collections.abc.Iterable):
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return "".join(_printnode(ns, at, level, n, target_filter) for n in node)
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return "".join(_print_node(ns, at, level, n, target_filter) for n in node)
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
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r += _printnode(ns, at, level + 1, node.t, target_filter)
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r = "\t"*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n"
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r += _print_node(ns, at, level + 1, node.t, target_filter)
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if node.f:
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r += "\t"*level + "end else begin\n"
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r += _printnode(ns, at, level + 1, node.f, target_filter)
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r += _print_node(ns, at, level + 1, node.f, target_filter)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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if node.cases:
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r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
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r = "\t"*level + "case (" + _print_expression(ns, node.test)[0] + ")\n"
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css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
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css = sorted(css, key=lambda x: x[0].value)
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for choice, statements in css:
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r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
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r += _printnode(ns, at, level + 2, statements, target_filter)
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r += "\t"*(level + 1) + _print_expression(ns, choice)[0] + ": begin\n"
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r += _print_node(ns, at, level + 2, statements, target_filter)
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r += "\t"*(level + 1) + "end\n"
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if "default" in node.cases:
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r += "\t"*(level + 1) + "default: begin\n"
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r += _printnode(ns, at, level + 2, node.cases["default"], target_filter)
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r += _print_node(ns, at, level + 2, node.cases["default"], target_filter)
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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@ -226,9 +225,9 @@ def _printnode(ns, at, level, node, target_filter=None):
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else:
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raise TypeError("Node of unrecognized type: "+str(type(node)))
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# Print Attributes ---------------------------------------------------------------------------------
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# Print Attribute ----------------------------------------------------------------------------------
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def _printattr(attr, attr_translate):
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def _print_attribute(attr, attr_translate):
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r = ""
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firsta = True
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for attr in sorted(attr,
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@ -251,7 +250,7 @@ def _printattr(attr, attr_translate):
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r = "(* " + r + " *)"
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return r
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# Print Header -------------------------------------------------------------------------------------
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# Print Module -------------------------------------------------------------------------------------
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def _list_comb_wires(f):
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r = set()
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@ -261,7 +260,7 @@ def _list_comb_wires(f):
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r |= g[0]
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return r
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def _printheader(f, ios, name, ns, attr_translate,
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def _print_module(f, ios, name, ns, attr_translate,
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reg_initialization):
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sigs = list_signals(f) | list_special_ios(f, True, True, True)
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special_outs = list_special_ios(f, False, True, True)
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@ -274,42 +273,42 @@ def _printheader(f, ios, name, ns, attr_translate,
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if not firstp:
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r += ",\n"
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firstp = False
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attr = _printattr(sig.attr, attr_translate)
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attr = _print_attribute(sig.attr, attr_translate)
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if attr:
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r += "\t" + attr
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sig.type = "wire"
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sig.name = ns.get_name(sig)
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if sig in inouts:
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sig.direction = "inout"
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r += "\tinout wire " + _printsig(ns, sig)
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r += "\tinout wire " + _print_signal(ns, sig)
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elif sig in targets:
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sig.direction = "output"
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if sig in wires:
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r += "\toutput wire " + _printsig(ns, sig)
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r += "\toutput wire " + _print_signal(ns, sig)
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else:
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sig.type = "reg"
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r += "\toutput reg " + _printsig(ns, sig)
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r += "\toutput reg " + _print_signal(ns, sig)
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else:
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sig.direction = "input"
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r += "\tinput wire " + _printsig(ns, sig)
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r += "\tinput wire " + _print_signal(ns, sig)
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r += "\n);\n\n"
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for sig in sorted(sigs - ios, key=lambda x: x.duid):
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attr = _printattr(sig.attr, attr_translate)
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attr = _print_attribute(sig.attr, attr_translate)
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if attr:
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r += attr + " "
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if sig in wires:
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r += "wire " + _printsig(ns, sig) + ";\n"
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r += "wire " + _print_signal(ns, sig) + ";\n"
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else:
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if reg_initialization:
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r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
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r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "reg " + _print_signal(ns, sig) + ";\n"
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r += "\n"
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return r
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# Print Combinatorial Logic (Simulation) -----------------------------------------------------------
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def _printcomb_simulation(f, ns,
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def _print_combinatorial_logic_sim(f, ns,
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display_run,
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dummy_signal,
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blocking_assign):
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@ -322,7 +321,7 @@ def _printcomb_simulation(f, ns,
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syn_on = "// synthesis translate_on\n"
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dummy_s = Signal(name_override="dummy_s")
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r += syn_off
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "reg " + _print_signal(ns, dummy_s) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
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r += syn_on
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@ -341,23 +340,23 @@ def _printcomb_simulation(f, ns,
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for n, (t, stmts) in enumerate(target_stmt_map.items()):
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assert isinstance(t, Signal)
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if len(stmts) == 1 and isinstance(stmts[0], _Assign):
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r += "assign " + _printnode(ns, _AT_BLOCKING, 0, stmts[0])
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r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0])
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else:
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if dummy_signal:
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dummy_d = Signal(name_override="dummy_d")
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r += "\n" + syn_off
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += "reg " + _print_signal(ns, dummy_d) + ";\n"
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r += syn_on
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r += "always @(*) begin\n"
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if display_run:
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r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
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if blocking_assign:
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r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_BLOCKING, 1, stmts, t)
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r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
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r += _print_node(ns, _AT_BLOCKING, 1, stmts, t)
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else:
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r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_NONBLOCKING, 1, stmts, t)
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r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
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r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t)
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if dummy_signal:
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " = " + ns.get_name(dummy_s) + ";\n"
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@ -368,45 +367,45 @@ def _printcomb_simulation(f, ns,
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# Print Combinatorial Logic (Synthesis) ------------------------------------------------------------
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def _printcomb_regular(f, ns, blocking_assign):
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def _print_combinatorial_logic_synth(f, ns, blocking_assign):
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r = ""
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if f.comb:
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groups = group_by_targets(f.comb)
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for n, g in enumerate(groups):
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
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r += "assign " + _print_node(ns, _AT_BLOCKING, 0, g[1][0])
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else:
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r += "always @(*) begin\n"
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if blocking_assign:
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_BLOCKING, 1, g[1])
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r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
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r += _print_node(ns, _AT_BLOCKING, 1, g[1])
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else:
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
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r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
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r += _print_node(ns, _AT_NONBLOCKING, 1, g[1])
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r += "end\n"
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r += "\n"
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return r
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# Print Synchronous Logic --------------------------------------------------------------------------
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def _printsync(f, ns):
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def _print_synchronous_logic(f, ns):
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r = ""
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for k, v in sorted(f.sync.items(), key=itemgetter(0)):
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r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
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r += _printnode(ns, _AT_SIGNAL, 1, v)
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r += _print_node(ns, _AT_SIGNAL, 1, v)
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r += "end\n\n"
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return r
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# Print Specials -----------------------------------------------------------------------------------
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def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
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def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
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r = ""
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for special in sorted(specials, key=lambda x: x.duid):
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if hasattr(special, "attr"):
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attr = _printattr(special.attr, attr_translate)
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attr = _print_attribute(special.attr, attr_translate)
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if attr:
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r += attr + " "
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# Replace Migen Memory's emit_verilog with our implementation.
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@ -419,7 +418,7 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
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r += pr
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return r
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# Convert FHDL to Verilog ------------------------------------------------------------------------
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# Convert FHDL to Verilog --------------------------------------------------------------------------
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class DummyAttrTranslate(dict):
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def __getitem__(self, k):
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@ -472,18 +471,18 @@ def convert(f, ios=None, name="top",
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r.ns = ns
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src = generated_banner("//")
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src += _printheader(f, ios, name, ns, attr_translate,
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src += _print_module(f, ios, name, ns, attr_translate,
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reg_initialization=reg_initialization)
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if regular_comb:
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src += _printcomb_regular(f, ns,
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src += _print_combinatorial_logic_synth(f, ns,
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blocking_assign=blocking_assign)
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else:
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src += _printcomb_simulation(f, ns,
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src += _print_combinatorial_logic_sim(f, ns,
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display_run=display_run,
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dummy_signal=dummy_signal,
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blocking_assign=blocking_assign)
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src += _printsync(f, ns)
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src += _printspecials(special_overrides, f.specials - lowered_specials,
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src += _print_synchronous_logic(f, ns)
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src += _print_specials(special_overrides, f.specials - lowered_specials,
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ns, r.add_data_file, attr_translate)
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src += "endmodule\n"
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r.set_main_source(src)
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