Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)

This commit is contained in:
Florent Kermarrec 2015-06-10 12:15:59 +02:00
parent 571ce5791a
commit a1f7ecc8c5
4 changed files with 32 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
misoclib/mem/litesata/doc/source/docs/intro/about.rst
View File

@ -4,7 +4,7 @@
About LiteSATA About LiteSATA
============== ==============
LiteSATA provides a small footprint and configurable SATA gen1/2 core. LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of the MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in modern SoCs such as Ethernet, SATA, PCIe, SDRAM controller... LiteSATA is part of the MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in modern SoCs such as Ethernet, SATA, PCIe, SDRAM controller...

24
misoclib/mem/litesata/example_designs/targets/bist.py
View File

@ -38,8 +38,8 @@ class CRG(Module):
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 166MHz # 200MHz
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
@ -56,6 +56,11 @@ class CRG(Module):
class StatusLeds(Module): class StatusLeds(Module):
def __init__(self, platform, sata_phys): def __init__(self, platform, sata_phys):
if not isinstance(sata_phys, list):
sata_phys = [sata_phys]
use_cd_num = False
else:
use_cd_num = True
for i, sata_phy in enumerate(sata_phys): for i, sata_phy in enumerate(sata_phys):
# 1Hz blinking leds (sata_rx and sata_tx clocks) # 1Hz blinking leds (sata_rx and sata_tx clocks)
rx_led = platform.request("user_led", 2*i) rx_led = platform.request("user_led", 2*i)
@ -64,7 +69,8 @@ class StatusLeds(Module):
freq = int(frequencies[sata_phy.revision]*1000*1000) freq = int(frequencies[sata_phy.revision]*1000*1000)
self.sync.sata_rx += \ rx_sync = getattr(self.sync, "sata_rx{}".format(str(i) if use_cd_num else ""))
rx_sync += \
If(rx_cnt == 0, If(rx_cnt == 0,
rx_led.eq(~rx_led), rx_led.eq(~rx_led),
rx_cnt.eq(freq//2) rx_cnt.eq(freq//2)
@ -83,7 +89,7 @@ class BISTSoC(SoC, AutoCSR):
} }
csr_map.update(SoC.csr_map) csr_map.update(SoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
clk_freq = 166*1000000 clk_freq = 200*1000000
SoC.__init__(self, platform, clk_freq, SoC.__init__(self, platform, clk_freq,
cpu_type="none", cpu_type="none",
with_csr=True, csr_data_width=32, with_csr=True, csr_data_width=32,
@ -96,19 +102,19 @@ class BISTSoC(SoC, AutoCSR):
self.submodules.crg = CRG(platform) self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend # SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq) self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
self.submodules.sata_core = LiteSATACore(self.sata_phy) self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True) self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
# Status Leds # Status Leds
self.submodules.leds = BISTLeds(platform, [self.sata_phy]) self.submodules.leds = StatusLeds(platform, self.sata_phy)
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk] create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk] create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk] create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]

16
misoclib/mem/litesata/example_designs/targets/mirroring.py
View File

@ -31,7 +31,7 @@ class MirroringSoC(SoC, AutoCSR):
} }
csr_map.update(SoC.csr_map) csr_map.update(SoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
clk_freq = 166*1000000 clk_freq = 200*1000000
SoC.__init__(self, platform, clk_freq, SoC.__init__(self, platform, clk_freq,
cpu_type="none", cpu_type="none",
with_csr=True, csr_data_width=32, with_csr=True, csr_data_width=32,
@ -44,10 +44,10 @@ class MirroringSoC(SoC, AutoCSR):
self.submodules.crg = CRG(platform) self.submodules.crg = CRG(platform)
# SATA PHYs # SATA PHYs
sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq) sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen2", clk_freq) sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen3", clk_freq)
sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen2", clk_freq) sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen3", clk_freq)
sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen2", clk_freq) sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen3", clk_freq)
sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3] sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
for i, sata_phy in enumerate(sata_phys): for i, sata_phy in enumerate(sata_phys):
sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)), sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
@ -79,13 +79,13 @@ class MirroringSoC(SoC, AutoCSR):
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk] create_clock -name sys_clk -period 5 [get_nets sys_clk]
""") """)
for i in range(len(sata_phys)): for i in range(len(sata_phys)):
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period 6.66 [get_nets {sata_rx_clk}] create_clock -name {sata_rx_clk} -period 3.33 [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period 6.66 [get_nets {sata_tx_clk}] create_clock -name {sata_tx_clk} -period 3.33 [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}] set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}] set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]

16
misoclib/mem/litesata/example_designs/targets/striping.py
View File

@ -28,7 +28,7 @@ class StripingSoC(SoC, AutoCSR):
} }
csr_map.update(SoC.csr_map) csr_map.update(SoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
clk_freq = 166*1000000 clk_freq = 200*1000000
SoC.__init__(self, platform, clk_freq, SoC.__init__(self, platform, clk_freq,
cpu_type="none", cpu_type="none",
with_csr=True, csr_data_width=32, with_csr=True, csr_data_width=32,
@ -41,10 +41,10 @@ class StripingSoC(SoC, AutoCSR):
self.submodules.crg = CRG(platform) self.submodules.crg = CRG(platform)
# SATA PHYs # SATA PHYs
sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq) sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen2", clk_freq) sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen3", clk_freq)
sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen2", clk_freq) sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen3", clk_freq)
sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen2", clk_freq) sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen3", clk_freq)
sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3] sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
for i, sata_phy in enumerate(sata_phys): for i, sata_phy in enumerate(sata_phys):
sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)), sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
@ -70,13 +70,13 @@ class StripingSoC(SoC, AutoCSR):
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk] create_clock -name sys_clk -period 5 [get_nets sys_clk]
""") """)
for i in range(len(sata_phys)): for i in range(len(sata_phys)):
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period 6.66 [get_nets {sata_rx_clk}] create_clock -name {sata_rx_clk} -period 3.33 [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period 6.66 [get_nets {sata_tx_clk}] create_clock -name {sata_tx_clk} -period 3.33 [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}] set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}] set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]