Merge branch 'master' of https://github.com/m-labs/migen

migen/sim/generic.py

@@ -87,11 +87,11 @@ class Simulator:
 		c_top = self.top_level.get(sockaddr)
 
 		fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
-		c_fragment, self.namespace = verilog.convert(fragment,
+		c_fragment = verilog.convert(fragment,
 			ios=self.top_level.ios,
 			name=self.top_level.dut_type,
-			return_ns=True,
 			**vopts)
+		self.namespace = c_fragment.ns
 
 		self.cycle_counter = -1
 

migen/sim/icarus.py

@@ -5,10 +5,6 @@ import subprocess
 import os
 import time
 
-def _str2file(filename, contents):
-	f = open(filename, "w")
-	f.write(contents)
-	f.close()
 
 class Runner:
 	def __init__(self, options=None, extra_files=None, top_file="migensim_top.v", dut_file="migensim_dut.v", vvp_file=None, keep_files=False):
@@ -20,11 +16,14 @@ class Runner:
 		self.top_file = top_file
 		self.dut_file = dut_file
 		self.vvp_file = vvp_file
+		self.data_files = []
 		self.keep_files = keep_files
 
 	def start(self, c_top, c_dut):
-		_str2file(self.top_file, c_top)
-		_str2file(self.dut_file, c_dut)
+		with open(self.top_file, "w") as f:
+			f.write(c_top)
+		c_dut.write(self.dut_file)
+		self.data_files += c_dut.data_files.keys()
 		subprocess.check_call(["iverilog", "-o", self.vvp_file] + self.options + [self.top_file, self.dut_file] + self.extra_files)
 		self.process = subprocess.Popen(["vvp", "-mmigensim", "-Mvpi", self.vvp_file])
 
@@ -36,8 +35,9 @@ class Runner:
 				self.process.kill()
 			self.process.wait()
 		if not self.keep_files:
-			for f in [self.top_file, self.dut_file, self.vvp_file]:
+			for f in [self.top_file, self.dut_file, self.vvp_file] + self.data_files:
 				try:
 					os.remove(f)
 				except OSError:
 					pass
+		self.data_files.clear()