cpu/naxriscv Add pythondata support
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Dolu1990
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d0dc5c8d95
commit
a3243e32ec
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@ -1,46 +0,0 @@
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module Ram_1w_1rs #(
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parameter integer wordCount = 0,
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parameter integer wordWidth = 0,
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parameter clockCrossing = 1'b0,
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parameter technology = "auto",
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parameter readUnderWrite = "dontCare",
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parameter integer wrAddressWidth = 0,
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parameter integer wrDataWidth = 0,
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parameter integer wrMaskWidth = 0,
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parameter wrMaskEnable = 1'b0,
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parameter integer rdAddressWidth = 0,
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parameter integer rdDataWidth = 0
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)(
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input wr_clk,
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input wr_en,
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input [wrMaskWidth-1:0] wr_mask,
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input [wrAddressWidth-1:0] wr_addr,
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input [wrDataWidth-1:0] wr_data,
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input rd_clk,
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input rd_en,
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input [rdAddressWidth-1:0] rd_addr,
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output [rdDataWidth-1:0] rd_data
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);
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reg [wrDataWidth-1:0] ram_block [(2**wrAddressWidth)-1:0];
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integer i;
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localparam COL_WIDTH = wrDataWidth/wrMaskWidth;
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always @ (posedge wr_clk) begin
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if(wr_en) begin
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for(i=0;i<wrMaskWidth;i=i+1) begin
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if(wr_mask[i]) begin
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ram_block[wr_addr][i*COL_WIDTH +: COL_WIDTH] <= wr_data[i*COL_WIDTH +:COL_WIDTH];
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end
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end
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end
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end
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reg [rdDataWidth-1:0] ram_rd_data;
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always @ (posedge rd_clk) begin
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if(rd_en) begin
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ram_rd_data <= ram_block[rd_addr];
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end
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end
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assign rd_data = ram_rd_data;
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endmodule
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@ -4,12 +4,14 @@
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2022 Dolu1990 <charles.papon.90@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import hashlib
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import os
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import subprocess
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from os import path
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import axi
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from litex.soc.interconnect.csr import *
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@ -42,6 +44,9 @@ class NaxRiscv(CPU):
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# Default parameters.
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with_fpu = False
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with_rvc = False
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scala_files = ["misc.scala", "fetch.scala", "frontend.scala", "branch_predictor_std.scala", "lsu.scala", "eu_2alu_1share.scala"]
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netlist_name = None
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scala_paths = []
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# ABI.
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@staticmethod
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@ -81,6 +86,20 @@ class NaxRiscv(CPU):
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flags += f" -DUART_POLLING"
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return flags
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# Command line configuration arguments.
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@staticmethod
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def args_fill(parser):
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cpu_group = parser.add_argument_group("cpu")
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cpu_group.add_argument("--scala-file", action='append', help="Specify the scala files used to configure NaxRiscv")
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@staticmethod
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def args_read(args):
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print(args)
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if args.scala_file:
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NaxRiscv.scala_files = args.scala_file
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def __init__(self, platform, variant):
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self.platform = platform
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self.variant = "standard"
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@ -140,14 +159,90 @@ class NaxRiscv(CPU):
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self.reset_address = reset_address
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assert reset_address == 0x00000000
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@staticmethod
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def find_scala_files():
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vdir = get_data_mod("cpu", "naxriscv").data_location
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for file in NaxRiscv.scala_files:
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if os.path.exists(file):
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NaxRiscv.scala_paths.append(os.path.abspath(file))
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else:
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path = os.path.join(vdir, "configs", file)
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if os.path.exists(path):
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NaxRiscv.scala_paths.append(path)
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else:
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raise Exception(f"Can't find NaxRiscv's {file}")
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# Cluster Name Generation.
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@staticmethod
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def generate_netlist_name():
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md5_hash = hashlib.md5()
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for file in NaxRiscv.scala_paths:
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a_file = open(file, "rb")
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content = a_file.read()
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md5_hash.update(content)
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digest = md5_hash.hexdigest()
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NaxRiscv.netlist_name = "NaxRiscvLitex_" + digest
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@staticmethod
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def git_setup(name, dir, repo, hash):
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if not os.path.exists(dir):
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# Clone Repo.
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print(f"Cloning {name} Git repository...")
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subprocess.check_call("git clone {url} {options}".format(
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url = repo,
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options = dir
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), shell=True)
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# Use specific SHA1 (Optional).
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os.chdir(os.path.join(dir))
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os.system(f"cd {dir} && git checkout {hash}")
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# Netlist Generation.
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@staticmethod
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def generate_netlist():
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vdir = get_data_mod("cpu", "naxriscv").data_location
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ndir = os.path.join(vdir, "ext", "NaxRiscv")
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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# NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "c883e74e")
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# NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "10cfe066")
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gen_args = []
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gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
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gen_args.append(f"--netlist-directory={vdir}")
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for file in NaxRiscv.scala_paths:
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gen_args.append(f"--scala-file={file}")
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cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.LitexGen {" ".join(gen_args)}\""""
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print("NaxRiscv generation command :")
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print(cmd)
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if os.system(cmd) != 0:
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raise OSError('Failed to run sbt')
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def add_sources(self, platform):
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cdir = os.path.abspath(os.path.dirname(__file__))
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# FIXME: Create pythondata-cpu-naxriscv once working.
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if not os.path.exists(f"{cdir}/NaxRiscvLitex.v"):
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os.system(f"wget https://github.com/enjoy-digital/litex_naxriscv_test/files/8059827/NaxRiscvLitex.v.txt -P {cdir}")
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os.system(f"mv {cdir}/NaxRiscvLitex.v.txt {cdir}/NaxRiscvLitex.v")
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platform.add_source(os.path.join(cdir, "NaxRiscvLitex.v"))
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platform.add_source(os.path.join(cdir, "RamXilinx.v"))
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vdir = get_data_mod("cpu", "naxriscv").data_location
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print(f"NaxRiscv netlist : {self.netlist_name}")
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if not path.exists(os.path.join(vdir, self.netlist_name + ".v")):
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self.generate_netlist()
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# Add RAM.
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# By default, use Generic RAM implementation.
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ram_filename = "Ram_1w_1rs_Generic.v"
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# On Altera/Intel platforms, use specific implementation.
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from litex.build.altera import AlteraPlatform
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if isinstance(platform, AlteraPlatform):
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ram_filename = "Ram_1w_1rs_Intel.v"
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# On Efinix platforms, use specific implementation.
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from litex.build.efinix import EfinixPlatform
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if isinstance(platform, EfinixPlatform):
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ram_filename = "Ram_1w_1rs_Efinix.v"
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platform.add_source(os.path.join(vdir, ram_filename), "verilog")
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# Add Cluster.
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platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog")
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def add_soc_components(self, soc, soc_region_cls):
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soc.csr.add("uart", n=2)
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@ -272,8 +367,13 @@ class NaxRiscv(CPU):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.find_scala_files()
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self.generate_netlist_name()
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# Do verilog instance.
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self.specials += Instance("NaxRiscvLitex", **self.cpu_params)
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self.specials += Instance(self.netlist_name, **self.cpu_params)
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# Add verilog sources
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self.add_sources(self.platform)
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@ -99,6 +99,7 @@ git_repos = {
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"pythondata-cpu-serv": GitRepo(url="https://github.com/litex-hub/"),
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"pythondata-cpu-vexriscv": GitRepo(url="https://github.com/litex-hub/"),
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"pythondata-cpu-vexriscv-smp": GitRepo(url="https://github.com/litex-hub/", clone="recursive"),
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"pythondata-cpu-naxriscv": GitRepo(url="https://github.com/litex-hub/"),
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"pythondata-cpu-rocket": GitRepo(url="https://github.com/litex-hub/"),
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"pythondata-cpu-minerva": GitRepo(url="https://github.com/litex-hub/"),
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"pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb940b55acff),
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