cores/cpu: define CPUS and simplify instance
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@ -11,6 +11,18 @@ from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.serv import SERV
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from litex.soc.cores.cpu.serv import SERV
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# CPUS ---------------------------------------------------------------------------------------------
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CPUS = {
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"lm32" : LM32,
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"mor1kx" : MOR1KX,
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"picorv32" : PicoRV32,
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"vexriscv" : VexRiscv,
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"minerva" : Minerva,
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"rocket" : RocketRV64,
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"serv" : SERV
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}
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# CPU Variants/Extensions Definition ---------------------------------------------------------------
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# CPU Variants/Extensions Definition ---------------------------------------------------------------
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CPU_VARIANTS = {
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CPU_VARIANTS = {
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@ -264,25 +264,9 @@ class SoCCore(Module):
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if cpu_variant is not None:
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if cpu_variant is not None:
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self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
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self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
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# CPU selection / instance
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# CPU selection / instance
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if cpu_type == "lm32":
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if cpu_type not in cpu.CPUS.keys():
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self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "mor1kx" or cpu_type == "or1k":
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if cpu_type == "or1k":
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deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
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self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "picorv32":
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self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "vexriscv":
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self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "minerva":
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self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "rocket":
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self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
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elif cpu_type == "serv":
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self.add_cpu(cpu.serv.SERV(platform, self.cpu_reset_address, self.cpu_variant))
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self.add_constant("UART_POLLING", None)
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else:
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raise ValueError("Unsupported CPU type: {}".format(cpu_type))
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raise ValueError("Unsupported CPU type: {}".format(cpu_type))
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self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_reset_address, self.cpu_variant))
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# Add Instruction/Data buses as Wisbone masters
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# Add Instruction/Data buses as Wisbone masters
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self.add_wb_master(self.cpu.ibus)
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self.add_wb_master(self.cpu.ibus)
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