Merge branch 'master' of https://github.com/m-labs/misoc
This commit is contained in:
Sebastien Bourdeauducq
commit
a3909bb5e2
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@ -1,6 +1,4 @@
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import os
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from operator import itemgetter
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from collections import defaultdict
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from math import ceil
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from migen.fhdl.std import *
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@ -13,6 +11,9 @@ from misoclib.sdram import lasmicon
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from misoclib.sdram import dfii
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from misoclib.sdram.minicon import Minicon
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def mem_decoder(address, start=26, end=29):
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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class GenSoC(Module):
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csr_map = {
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"crg": 0, # user
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@ -26,13 +27,11 @@ class GenSoC(Module):
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"uart": 0,
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"timer0": 1,
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}
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known_platform_id = defaultdict(lambda: 0x554E, {
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"mixxeo": 0x4D58,
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"m1": 0x4D31,
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"papilio_pro": 0x5050,
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"kc705": 0x4B37
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})
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mem_map = {
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"rom": 0x00000000, # (shadow @0x80000000)
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"sram": 0x10000000, # (shadow @0x90000000)
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"csr": 0x60000000, # (shadow @0xe0000000)
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}
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def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32",
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csr_data_width=8, csr_address_width=14):
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self.clk_freq = clk_freq
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@ -48,9 +47,9 @@ class GenSoC(Module):
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# Wishbone
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if cpu_type == "lm32":
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self.submodules.cpu = lm32.LM32(cpu_reset_address)
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self.submodules.cpu = lm32.LM32(platform, cpu_reset_address)
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elif cpu_type == "or1k":
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self.submodules.cpu = mor1kx.MOR1KX(cpu_reset_address)
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self.submodules.cpu = mor1kx.MOR1KX(platform, cpu_reset_address)
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else:
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raise ValueError("Unsupported CPU type: "+cpu_type)
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self.submodules.sram = wishbone.SRAM(sram_size)
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@ -61,36 +60,25 @@ class GenSoC(Module):
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# CSR bridge 0x60000000 (shadow @0xe0000000) provided
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self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
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self._wb_slaves = [
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(lambda a: a[26:29] == 1, self.sram.bus),
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(lambda a: a[26:29] == 6, self.wishbone2csr.wishbone)
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(mem_decoder(self.mem_map["sram"]), self.sram.bus),
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(mem_decoder(self.mem_map["csr"]), self.wishbone2csr.wishbone)
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]
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self.add_cpu_memory_region("sram", 0x10000000, sram_size)
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self.add_cpu_memory_region("sram", self.mem_map["sram"], sram_size)
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# CSR
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if with_uart:
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq),
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platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
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self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq),
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log2_int(l2_size) if l2_size else 0)
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self.submodules.timer0 = timer.Timer()
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# add CPU Verilog sources
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if cpu_type == "lm32":
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platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
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"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
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if cpu_type == "or1k":
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platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
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def register_rom(self, rom_wb_if, bios_size=0xa000):
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if self._rom_registered:
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raise FinalizeError
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self._rom_registered = True
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self.add_wb_slave(lambda a: a[26:29] == 0, rom_wb_if)
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self.add_wb_slave(mem_decoder(self.mem_map["rom"]), rom_wb_if)
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self.add_cpu_memory_region("rom", self.cpu_reset_address, bios_size)
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def add_wb_master(self, wbm):
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@ -123,9 +111,9 @@ class GenSoC(Module):
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data_width=self.csr_data_width, address_width=self.csr_address_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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# Interrupts
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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@ -158,6 +146,11 @@ class SDRAMSoC(GenSoC):
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}
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csr_map.update(GenSoC.csr_map)
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mem_map = {
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"sdram": 0x40000000, # (shadow @0xc0000000)
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}
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mem_map.update(GenSoC.mem_map)
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def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True, ramcon_type="lasmicon", **kwargs):
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GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart, **kwargs)
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self.with_memtest = with_memtest
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@ -174,8 +167,8 @@ class SDRAMSoC(GenSoC):
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phy_settings.dfi_d, phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
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# LASMICON
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if self.ramcon_type == "lasmicon":
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# LASMI
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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@ -185,27 +178,28 @@ class SDRAMSoC(GenSoC):
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
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# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
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# Wishbone bridge
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
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self.add_wb_slave(lambda a: a[26:29] == 4, self.wishbone2lasmi.wishbone)
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self.add_cpu_memory_region("sdram", 0x40000000,
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.wishbone2lasmi.wishbone)
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self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
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2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
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# MINICON
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elif self.ramcon_type == "minicon":
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self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
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sdram_width = flen(sdramcon.bus.dat_r)
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if (sdram_width == 32):
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self.add_wb_slave(lambda a: a[26:29] == 4, sdramcon.bus)
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
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elif (sdram_width < 32):
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self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width)
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self.submodules.dc = wishbone.DownConverter(32, sdram_width)
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self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
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self.add_wb_slave(lambda a: a[26:29] == 4, dc.wishbone_i)
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
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else:
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raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
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# map SDRAM at 0x40000000 (shadow @0xc0000000)
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self.add_cpu_memory_region("sdram", 0x40000000,
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# Wishbone bridge
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self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
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2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8)
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else:
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raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
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@ -1,8 +1,10 @@
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import os
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from migen.fhdl.std import *
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from migen.bus import wishbone
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class LM32(Module):
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def __init__(self, eba_reset):
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def __init__(self, platform, eba_reset):
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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@ -49,3 +51,12 @@ class LM32(Module):
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self.ibus.adr.eq(i_adr_o[2:]),
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self.dbus.adr.eq(d_adr_o[2:])
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]
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# add Verilog sources
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platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
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"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
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@ -1,8 +1,10 @@
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import os
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from migen.fhdl.std import *
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from migen.bus import wishbone
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class MOR1KX(Module):
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def __init__(self, reset_pc):
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def __init__(self, platform, reset_pc):
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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@ -71,3 +73,6 @@ class MOR1KX(Module):
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self.ibus.adr.eq(i_adr_o[2:]),
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self.dbus.adr.eq(d_adr_o[2:])
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]
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# add Verilog sources
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platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
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@ -3,7 +3,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoclib import sdram, spiflash
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from misoclib.sdram.phy import k7ddrphy
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from misoclib.gensoc import SDRAMSoC
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from misoclib.gensoc import SDRAMSoC, mem_decoder
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from misoclib.liteeth.phy.gmii import LiteEthPHYGMII
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from misoclib.liteeth.mac import LiteEthMAC
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@ -120,12 +120,17 @@ class MiniSoC(BaseSoC):
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
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default_subtarget = BaseSoC
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@ -6,7 +6,7 @@ from mibuild.generic_platform import ConstraintError
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from misoclib import sdram, mxcrg, norflash16, framebuffer, gpio
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from misoclib.sdram.phy import s6ddrphy
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from misoclib.gensoc import SDRAMSoC
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from misoclib.gensoc import SDRAMSoC, mem_decoder
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from misoclib.liteeth.phy.mii import LiteEthPHYMII
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from misoclib.liteeth.mac import LiteEthMAC
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@ -84,6 +84,11 @@ class MiniSoC(BaseSoC):
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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@ -95,8 +100,8 @@ class MiniSoC(BaseSoC):
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self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
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def get_vga_dvi(platform):
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try:
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@ -1,7 +1,7 @@
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC, IntegratedBIOS
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from misoclib.gensoc import GenSoC, IntegratedBIOS, mem_decoder
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class _CRG(Module):
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def __init__(self, clk_in):
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@ -18,6 +18,11 @@ class _CRG(Module):
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]
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class SimpleSoC(GenSoC, IntegratedBIOS):
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mem_map = {
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"sdram": 0x40000000, # (shadow @0xc0000000)
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}
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mem_map.update(GenSoC.mem_map)
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def __init__(self, platform):
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GenSoC.__init__(self, platform,
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clk_freq=int((1/(platform.default_clk_period))*1000000000),
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@ -29,7 +34,7 @@ class SimpleSoC(GenSoC, IntegratedBIOS):
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# use on-board SRAM as SDRAM
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sys_ram_size = 16*1024
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self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
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self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
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self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.sys_ram.bus)
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self.add_cpu_memory_region("sdram", self.mem_map["sdram"], sys_ram_size)
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default_subtarget = SimpleSoC
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