tools/litex_sim: Fix missing update in ram_init.

2023-01-16 11:12:24 +01:00 · 2023-01-16 11:12:24 +01:00 · a39e2c836a
parent 5760c5ba1e
commit a39e2c836a
1 changed files with 1 additions and 1 deletions
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@ -490,7 +490,7 @@ def main():
        **soc_kwargs)
    if ram_boot_address is not None:
        if ram_boot_address == 0:
-            ram_boot_address = ram_boot_offset
+            ram_boot_address = conf_soc.mem_map["main_ram"]
        soc.add_constant("ROM_BOOT_ADDRESS", ram_boot_address)
    if args.with_ethernet:
        for i in range(4):