litex/soc/integration/soc: SoCBusHandler 64bits address width support

2023-11-30 17:47:32 +01:00 · 2023-11-30 17:47:32 +01:00 · a4ead5cab9
parent fba581f77e
commit a4ead5cab9
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -108,7 +108,7 @@ class SoCCSRRegion:
 class SoCBusHandler(LiteXModule):
    supported_standard      = ["wishbone", "axi-lite", "axi"]
    supported_data_width    = [32, 64, 128, 256, 512]
-    supported_address_width = [32]
+    supported_address_width = [32, 64]

    # Creation -------------------------------------------------------------------------------------
    def __init__(self, name="SoCBusHandler",