create utils directory and move the litex utils to it
This commit is contained in:
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45ec78e93a
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@ -1,64 +0,0 @@
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from litex.build.generic_platform import *
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from litex.build.sim import SimPlatform
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class SimPins(Pins):
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def __init__(self, n):
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Pins.__init__(self, "s "*n)
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_io = [
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("sys_clk", 0, SimPins(1)),
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("sys_rst", 0, SimPins(1)),
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("serial", 0,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 0,
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Subsignal("none", SimPins(1)),
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),
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("eth", 0,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 1,
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Subsignal("none", SimPins(1)),
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),
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("eth", 1,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("vga", 0,
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Subsignal("de", SimPins(1)),
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Subsignal("hsync", SimPins(1)),
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Subsignal("vsync", SimPins(1)),
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Subsignal("r", SimPins(8)),
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Subsignal("g", SimPins(8)),
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Subsignal("b", SimPins(8)),
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),
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]
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class Platform(SimPlatform):
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default_clk_name = "sys_clk"
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default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
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def __init__(self):
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SimPlatform.__init__(self, "SIM", _io)
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def do_finalize(self, fragment):
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pass
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@ -1,5 +1,4 @@
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from litex.soc.tools.remote.comm_uart import CommUART
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from litex.soc.tools.remote.comm_uart import CommUART
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from litex.soc.tools.remote.comm_udp import CommUDP
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from litex.soc.tools.remote.comm_udp import CommUDP
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from litex.soc.tools.remote.comm_pcie import CommPCIe
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from litex.soc.tools.remote.comm_pcie import CommPCIe
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from litex.soc.tools.remote.litex_server import RemoteServer
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from litex.soc.tools.remote.litex_client import RemoteClient
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from litex.soc.tools.remote.litex_client import RemoteClient
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2
litex/soc/tools/remote/litex_server.py → litex/utils/litex_server.py
Normal file → Executable file
2
litex/soc/tools/remote/litex_server.py → litex/utils/litex_server.py
Normal file → Executable file
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@ -1,3 +1,5 @@
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#!/usr/bin/env python3
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import sys
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import sys
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import socket
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import socket
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import time
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import time
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@ -5,7 +5,9 @@ import argparse
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from migen import *
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from migen import *
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from migen.genlib.io import CRG
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from migen.genlib.io import CRG
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from litex.boards.platforms import sim
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from litex.build.generic_platform import *
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.soc_sdram import *
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@ -26,7 +28,68 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
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from litescope import LiteScopeAnalyzer
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from litescope import LiteScopeAnalyzer
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from litex.build.sim.config import SimConfig
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class SimPins(Pins):
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def __init__(self, n):
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Pins.__init__(self, "s "*n)
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_io = [
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("sys_clk", 0, SimPins(1)),
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("sys_rst", 0, SimPins(1)),
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("serial", 0,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 0,
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Subsignal("none", SimPins(1)),
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),
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("eth", 0,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 1,
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Subsignal("none", SimPins(1)),
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),
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("eth", 1,
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Subsignal("source_valid", SimPins(1)),
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Subsignal("source_ready", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins(1)),
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Subsignal("sink_ready", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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("vga", 0,
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Subsignal("de", SimPins(1)),
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Subsignal("hsync", SimPins(1)),
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Subsignal("vsync", SimPins(1)),
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Subsignal("r", SimPins(8)),
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Subsignal("g", SimPins(8)),
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Subsignal("b", SimPins(8)),
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),
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]
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class Platform(SimPlatform):
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default_clk_name = "sys_clk"
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default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
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def __init__(self):
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SimPlatform.__init__(self, "SIM", _io)
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def do_finalize(self, fragment):
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pass
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def csr_map_update(csr_map, csr_peripherals):
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def csr_map_update(csr_map, csr_peripherals):
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@ -62,7 +125,7 @@ class SimSoC(SoCSDRAM):
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with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
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with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
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with_analyzer=False,
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with_analyzer=False,
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**kwargs):
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**kwargs):
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platform = sim.Platform()
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platform = Platform()
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sys_clk_freq = int(1e9/platform.default_clk_period)
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sys_clk_freq = int(1e9/platform.default_clk_period)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_rom_size=0x8000,
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@ -192,7 +192,7 @@ class LiteXTerm:
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print("[TERM] Booting the device.")
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print("[TERM] Booting the device.")
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frame = SFLFrame()
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frame = SFLFrame()
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frame.cmd = sfl_cmd_jump
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frame.cmd = sfl_cmd_jump
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frame.payload = self.kernel_address.to_bytes(4, "big")
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frame.payload = self.kernel_address.to_bytes(4, "big")
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self.send_frame(frame)
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self.send_frame(frame)
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def detect_prompt(self, data):
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def detect_prompt(self, data):
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6
setup.py
6
setup.py
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@ -37,9 +37,9 @@ setup(
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entry_points={
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entry_points={
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"console_scripts": [
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"console_scripts": [
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"mkmscimg=litex.soc.tools.mkmscimg:main",
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"mkmscimg=litex.soc.tools.mkmscimg:main",
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"litex_term=litex.soc.tools.litex_term:main",
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"litex_term=litex.utils.litex_term:main",
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"litex_server=litex.soc.tools.remote.litex_server:main",
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"litex_server=litex.utils.litex_server:main",
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"litex_sim=litex.boards.targets.sim:main",
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"litex_sim=litex.utils.litex_sim:main",
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"litex_simple=litex.boards.targets.simple:main",
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"litex_simple=litex.boards.targets.simple:main",
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],
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],
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},
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},
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