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utils/litex_sim: handle cpu_endianness for rom-init/ram-init

This commit is contained in:
Florent Kermarrec 2019-03-13 10:56:09 +01:00
parent 411bca790a
commit a549f0941b
1 changed files with 8 additions and 2 deletions
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10
litex/utils/litex_sim.py
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@ -215,12 +215,18 @@ def main():
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
cpu_endianness = "big"
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
cpu_endianness = "little"
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0