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hyperbus: check if cyc is active during every state

This commit is contained in:
Franck Jullien 2022-04-28 10:42:07 +02:00
parent 5220984df8
commit a66af6343e
1 changed files with 6 additions and 2 deletions
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8
litex/soc/cores/hyperbus.py
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@ -159,7 +159,9 @@ class HyperRAM(Module):
# Wait for 6*2 cycles... # Wait for 6*2 cycles...
If(cycles == (6*2 - 1), If(cycles == (6*2 - 1),
NextState("WAIT-LATENCY") NextState("WAIT-LATENCY")
) ),
# Always check if bus cycle is still active
If(~bus.cyc, NextState("IDLE"))
) )
fsm.act("WAIT-LATENCY", fsm.act("WAIT-LATENCY",
# Set CSn. # Set CSn.
@ -171,7 +173,9 @@ class HyperRAM(Module):
# Early Write Ack (to allow bursting). # Early Write Ack (to allow bursting).
bus.ack.eq(bus.we), bus.ack.eq(bus.we),
NextState("READ-WRITE-DATA0") NextState("READ-WRITE-DATA0")
) ),
# Always check if bus cycle is still active
If(~bus.cyc, NextState("IDLE"))
) )
states = {8:4, 16:2}[dw] states = {8:4, 16:2}[dw]
for n in range(states): for n in range(states):