Simple bus base class

migen/bus/csr.py

@@ -1,21 +1,20 @@
 from migen.fhdl import structure as f
-from functools import partial
+from .simple import Simple
 
-class Master:
+_desc = [
-	def __init__(self):
+	(True,	"a",	16),
-		d = partial(f.Declare, self)
+	(True,	"we",	1),
-		d("a_o", f.BV(16))
+	(True,	"d",	32),
-		d("we_o")
+	(False,	"d",	32)
-		d("d_o", f.BV(32))
+]
-		d("d_i", f.BV(32))
 
-class Slave:
+class Master(Simple):
 	def __init__(self):
-		d = partial(f.Declare, self)
+		Simple.__init__(self, _desc, False)
-		d("a_i", f.BV(16))
+
-		d("we_i")
+class Slave(Simple):
-		d("d_i", f.BV(32))
+	def __init__(self):
-		d("d_o", f.BV(32))
+		Simple.__init__(self, _desc, True)
 
 class Interconnect:
 	def __init__(self, master, slaves):
@@ -32,4 +31,4 @@ class Interconnect:
 			comb.append(a(slave.d_i, self.master.d_o))
 			rb = rb | slave.d_o
 		comb.append(a(master.d_i, rb))
-		return f.Fragment(comb)
+		return f.Fragment(comb)

migen/bus/simple.py

@@ -0,0 +1,17 @@
+from migen.fhdl import structure as f
+
+# desc is a list of tuples, each made up of:
+# 0) boolean: "master to slave"
+# 1) string: name
+# 2) int: width
+class Simple():
+	def __init__(self, desc, slave):
+		for signal in desc:
+			if signal[0] ^ slave:
+				suffix = "_o"
+			else:
+				suffix = "_i"
+			modules = self.__module__.split('.')
+			busname = modules[len(modules)-1]
+			signame = signal[1]+suffix
+			setattr(self, signame, f.Signal(f.BV(signal[2]), busname+"_"+signame))

migen/fhdl/structure.py

@@ -117,7 +117,7 @@ class Signal(Value):
 		return id(self)
 
 def Declare(parent, name, bv=BV(), variable=False, reset=0):
-	setattr(parent, name, Signal(bv, parent.__class__.__name__+"_"+name, variable, reset))
+	setattr(parent, name, Signal(bv, parent.__class__.__name__ + "_" + name, variable, reset))
 
 # statements