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Merge pull request #891 from antmicro/crosslink-nx-fix-sdr-buffers 

Lattice Crosslink NX: Fix clock port names in SDR{in/out} Impl
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enjoy-digital 2021-04-26 11:19:44 +02:00 committed by GitHub
parent 65a4886b72 54f729fbc1
commit a6c5fd7aed
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1 changed files with 2 additions and 2 deletions
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litex/build/lattice/common.py
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@ -196,7 +196,7 @@ class LatticeNXAsyncResetSynchronizer:
class LatticeNXSDRInputImpl(Module): class LatticeNXSDRInputImpl(Module):
def __init__(self, i, o, clk): def __init__(self, i, o, clk):
self.specials += Instance("IFD1P3BX", self.specials += Instance("IFD1P3BX",
i_SCLK = clk, i_CK = clk,
i_PD = 0, i_PD = 0,
i_SP = 1, i_SP = 1,
i_D = i, i_D = i,
@ -213,7 +213,7 @@ class LatticeNXSDRInput:
class LatticeNXSDROutputImpl(Module): class LatticeNXSDROutputImpl(Module):
def __init__(self, i, o, clk): def __init__(self, i, o, clk):
self.specials += Instance("OFD1P3BX", self.specials += Instance("OFD1P3BX",
i_SCLK = clk, i_CK = clk,
i_PD = 0, i_PD = 0,
i_SP = 1, i_SP = 1,
i_D = i, i_D = i,