fhdl: allow a namespace to be specified for Verilog conversion

2011-12-13 00:24:40 +01:00 · 2011-12-13 00:24:40 +01:00 · a72faaecdd
parent eee6980a36
commit a72faaecdd
1 changed files with 4 additions and 4 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -115,8 +115,8 @@ def _printinstances(ns, i, clk, rst):
 		r += ");\n\n"
 	return r

-def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
-	ns = Namespace()
+def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst", ns=None):
+	if ns is None: ns = Namespace()

 	clks = Signal(name=clkname)
 	rsts = Signal(name=rstname)