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fhdl: allow a namespace to be specified for Verilog conversion

This commit is contained in:
Sebastien Bourdeauducq 2011-12-13 00:24:40 +01:00
parent eee6980a36
commit a72faaecdd
1 changed files with 4 additions and 4 deletions
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8
migen/fhdl/verilog.py
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@ -115,12 +115,12 @@ def _printinstances(ns, i, clk, rst):
r += ");\n\n"
return r
def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
ns = Namespace()
def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst", ns=None):
if ns is None: ns = Namespace()
clks = Signal(name=clkname)
rsts = Signal(name=rstname)
ios |= f.pads
sigs = ListSignals(f)