soc/add_uart: Fix uart_name="uartbone" case.

2022-01-20 10:09:16 +01:00 · 2022-01-20 10:09:16 +01:00 · a76828a40a
parent 928ee285dc
commit a76828a40a
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1249,8 +1249,8 @@ class LiteXSoC(SoC):
        # Add PHY/UART.
        if uart_phy is not None:
            setattr(self.submodules, name + "_phy", uart_phy)
-        assert uart is not None
-        setattr(self.submodules, name, uart)
+        if uart is not None:
+            setattr(self.submodules, name, uart)

        # IRQ.
        if self.irq.enabled: