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soc/add_uart: Fix uart_name="uartbone" case.

This commit is contained in:
Florent Kermarrec 2022-01-20 10:09:16 +01:00
parent 928ee285dc
commit a76828a40a
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -1249,8 +1249,8 @@ class LiteXSoC(SoC):
# Add PHY/UART. # Add PHY/UART.
if uart_phy is not None: if uart_phy is not None:
setattr(self.submodules, name + "_phy", uart_phy) setattr(self.submodules, name + "_phy", uart_phy)
assert uart is not None if uart is not None:
setattr(self.submodules, name, uart) setattr(self.submodules, name, uart)
# IRQ. # IRQ.
if self.irq.enabled: if self.irq.enabled: