soc/add_uart: Fix uart_name="uartbone" case.

litex/soc/integration/soc.py

@@ -1249,7 +1249,7 @@ class LiteXSoC(SoC):
         # Add PHY/UART.
         if uart_phy is not None:
             setattr(self.submodules, name + "_phy", uart_phy)
-        assert uart is not None
+        if uart is not None:
             setattr(self.submodules, name, uart)
 
         # IRQ.