Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/gpio: use separate TSTriple for each bit. 

This fixes per bit OE control.
This commit is contained in:
Florent Kermarrec 2020-02-28 09:10:28 +01:00
parent 400492e234
commit a7c5dd5d3e
1 changed files with 15 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
litex/soc/cores/gpio.py
View File

@ -34,12 +34,19 @@ class GPIOInOut(Module):
class GPIOTristate(Module, AutoCSR): class GPIOTristate(Module, AutoCSR):
def __init__(self, pads): def __init__(self, pads):
self._oe = CSRStorage(len(pads)) nbits = len(pads)
self._in = CSRStatus(len(pads)) self._oe = CSRStorage(nbits)
self._out = CSRStorage(len(pads)) self._in = CSRStatus(nbits)
self._out = CSRStorage(nbits)
t = TSTriple(len(pads)) # # #
self.specials += t.get_tristate(pads)
self.comb += t.oe.eq(self._oe.storage) _pads = Signal(nbits)
self.comb += t.o.eq(self._out.storage) self.comb += _pads.eq(pads)
self.specials += MultiReg(t.i, self._in.status)
for i in range(nbits):
t = TSTriple()
self.specials += t.get_tristate(_pads[i])
self.comb += t.oe.eq(self._oe.storage[i])
self.comb += t.o.eq(self._out.storage[i])
self.specials += MultiReg(t.i, self._in.status[i])