arp: rx and decoding OK
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@ -77,6 +77,13 @@ udp_header = {
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"checksum": HField( 6, 0, 16)
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"checksum": HField( 6, 0, 16)
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}
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}
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def reverse_bytes(v):
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n = math.ceil(flen(v)//8)
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r = []
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for i in reversed(range(n)):
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r.append(v[i*8:min((i+1)*8, flen(v))])
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return Cat(iter(r))
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# layouts
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# layouts
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def _layout_from_header(header):
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def _layout_from_header(header):
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_layout = []
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_layout = []
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@ -5,7 +5,7 @@ def _decode_header(h_dict, h_signal, obj):
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for k, v in sorted(h_dict.items()):
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for k, v in sorted(h_dict.items()):
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start = v.byte*8+v.offset
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start = v.byte*8+v.offset
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end = start+v.width
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end = start+v.width
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r.append(getattr(obj, k).eq(h_signal[start:end]))
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r.append(getattr(obj, k).eq(reverse_bytes(h_signal[start:end])))
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return r
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return r
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class LiteEthDepacketizer(Module):
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class LiteEthDepacketizer(Module):
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@ -18,6 +18,12 @@ class LiteEthDepacketizer(Module):
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counter = Counter(max=header_length)
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counter = Counter(max=header_length)
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self.submodules += counter
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self.submodules += counter
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self.sync += [
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If(shift,
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header.eq(Cat(header[8:], sink.data))
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)
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]
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.submodules += fsm
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@ -1,12 +1,4 @@
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from liteeth.common import *
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from liteeth.common import *
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import math
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def reverse_bytes(v):
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n = math.ceil(flen(v)//8)
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r = []
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for i in reversed(range(n)):
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r.append(v[i*8:min((i+1)*8, flen(v))])
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return Cat(iter(r))
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def _encode_header(h_dict, h_signal, obj):
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def _encode_header(h_dict, h_signal, obj):
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r = []
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r = []
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@ -51,4 +51,4 @@ class TB(Module):
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selfp.arp.table.request.stb = 1
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selfp.arp.table.request.stb = 1
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if __name__ == "__main__":
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=256, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
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