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fhdl/specials: allow setting memory name

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This commit is contained in:
Sebastien Bourdeauducq 2013-02-25 23:14:03 +01:00
parent 425de02f42
commit a81781f589
1 changed files with 2 additions and 3 deletions
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5
migen/fhdl/specials.py
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@ -180,12 +180,13 @@ class _MemoryPort:
self.clock_domain = clock_domain
class Memory(Special):
def __init__(self, width, depth, init=None):
def __init__(self, width, depth, init=None, name="mem"):
Special.__init__(self)
self.width = width
self.depth = depth
self.ports = []
self.init = init
self.name_override = name
def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST,
@ -234,8 +235,6 @@ class Memory(Special):
add(p.dat_r)
return s
name_override = "mem"
@staticmethod
def emit_verilog(memory, ns, clock_domains):
r = ""