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liteeth: pep8 (E225)

This commit is contained in:
Florent Kermarrec 2015-04-13 10:56:18 +02:00
parent 66ce40d880
commit a84f12618b
10 changed files with 14 additions and 14 deletions
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2
misoclib/com/liteeth/core/etherbone/record.py
View File

@ -174,7 +174,7 @@ class LiteEthEtherboneRecord(Module):
self.comb += [
Record.connect(sender.source, packetizer.sink),
Record.connect(packetizer.source, source),
source.length.eq(sender.source.wcount*4 + 4 +etherbone_record_header_len), # XXX improve this
source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len), # XXX improve this
source.ip_address.eq(last_ip_address)
]
if endianness is "big":

2
misoclib/com/liteeth/core/udp/crossbar.py
View File

@ -13,7 +13,7 @@ class LiteEthUDPMasterPort:
class LiteEthUDPSlavePort:
def __init__(self, dw):
self.dw =dw
self.dw = dw
self.sink = Sink(eth_udp_user_description(dw))
self.source = Source(eth_udp_user_description(dw))

4
misoclib/com/liteeth/example_designs/test/test_udp.py
View File

@ -26,7 +26,7 @@ def check(p1, p2):
else:
ref, res = p2, p1
shift = 0
while((ref[0] != res[0]) and (len(res)>1)):
while((ref[0] != res[0]) and (len(res) > 1)):
res.pop(0)
shift += 1
length = min(len(ref), len(res))
@ -59,7 +59,7 @@ def test(fpga_ip, udp_port, test_size):
rx_packet.append(int(byte))
rx_reference_packet, rx_seed = generate_packet(rx_seed, 1024)
s, l, e = check(rx_reference_packet, rx_packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
def send():
tx_seed = 0

2
misoclib/com/liteeth/mac/core/preamble.py
View File

@ -34,7 +34,7 @@ class LiteEthMACPreambleInserter(Module):
)
fsm.act("INSERT",
self.source.stb.eq(1),
self.source.sop.eq(cnt==0),
self.source.sop.eq(cnt == 0),
chooser(preamble, cnt, self.source.data),
If(cnt == cnt_max,
If(self.source.ack, NextState("COPY"))

8
misoclib/com/liteeth/phy/gmii_mii.py
View File

@ -33,7 +33,7 @@ class LiteEthPHYGMIIMIITX(Module):
demux = Demultiplexer(eth_phy_description(8), 2)
self.submodules += demux
self.comb += [
demux.sel.eq(mode==modes["MII"]),
demux.sel.eq(mode == modes["MII"]),
Record.connect(sink, demux.sink),
Record.connect(demux.source0, gmii_tx.sink),
Record.connect(demux.source1, mii_tx.sink),
@ -42,7 +42,7 @@ class LiteEthPHYGMIIMIITX(Module):
if hasattr(pads, "tx_er"):
self.comb += pads.tx_er.eq(0)
self.sync += [
If(mode==modes["MII"],
If(mode == modes["MII"],
pads.tx_en.eq(mii_tx_pads.tx_en),
pads.tx_data.eq(mii_tx_pads.tx_data),
).Else(
@ -71,7 +71,7 @@ class LiteEthPHYGMIIMIIRX(Module):
mux = Multiplexer(eth_phy_description(8), 2)
self.submodules += mux
self.comb += [
mux.sel.eq(mode==modes["MII"]),
mux.sel.eq(mode == modes["MII"]),
Record.connect(gmii_rx.source, mux.sink0),
Record.connect(mii_rx.source, mux.sink1),
Record.connect(mux.source, source)
@ -98,7 +98,7 @@ class LiteEthPHYGMIIMII(Module, AutoCSR):
self._mode = CSRStorage()
mode = self._mode.storage
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode==modes["MII"])
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
self.submodules.clock_counter = LiteEthGMIIMIIClockCounter()
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")

2
misoclib/com/liteeth/test/common.py
View File

@ -59,7 +59,7 @@ def check(p1, p2):
else:
ref, res = p2, p1
shift = 0
while((ref[0] != res[0]) and (len(res)>1)):
while((ref[0] != res[0]) and (len(res) > 1)):
res.pop(0)
shift += 1
length = min(len(ref), len(res))

2
misoclib/com/liteeth/test/etherbone_tb.py
View File

@ -111,7 +111,7 @@ class TB(Module):
# check results
s, l, e = check(writes_datas, loopback_writes_datas)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)

2
misoclib/com/liteeth/test/mac_core_tb.py
View File

@ -57,7 +57,7 @@ class TB(Module):
# check results
s, l, e = check(packet, self.logger.packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
run_simulation(TB(), ncycles=4000, vcd_name="my.vcd", keep_files=True)

2
misoclib/com/liteeth/test/mac_wishbone_tb.py
View File

@ -143,7 +143,7 @@ class TB(Module):
# check results
s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
run_simulation(TB(), ncycles=3000, vcd_name="my.vcd", keep_files=True)

2
misoclib/com/liteeth/test/udp_tb.py
View File

@ -62,7 +62,7 @@ class TB(Module):
# check results
s, l, e = check(packet, self.logger.packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":