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test/test_hyperbus: Update.

This commit is contained in:
Florent Kermarrec 2024-08-21 17:10:44 +02:00
parent 37823e34b6
commit a88cee70c8
1 changed files with 3 additions and 3 deletions
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6
test/test_hyperbus.py
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@ -169,9 +169,9 @@ class TestHyperBus(unittest.TestCase):
def test_hyperram_read_latency_5_2x(self): def test_hyperram_read_latency_5_2x(self):
def fpga_gen(dut): def fpga_gen(dut):
dat = yield from dut.bus.read(0x1234) dat = yield from dut.bus.read(0x1234)
#self.assertEqual(dat, 0xdeadbeef) self.assertEqual(dat, 0xdeadbeef)
dat = yield from dut.bus.read(0x1235) dat = yield from dut.bus.read(0x1235)
#self.assertEqual(dat, 0xcafefade) self.assertEqual(dat, 0xcafefade)
def hyperram_gen(dut): def hyperram_gen(dut):
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_" clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
@ -191,7 +191,7 @@ class TestHyperBus(unittest.TestCase):
yield yield
dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed") dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], {"sys": 4, "sys_2x": 2}, vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_read_latency_6_2x(self): def test_hyperram_read_latency_6_2x(self):
def fpga_gen(dut): def fpga_gen(dut):