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litex/soc/interconnect/wishbone.py: add data_width param

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tongchen126 2021-12-31 13:27:27 +08:00
parent e87e7ff31c
commit a8c8e4e3cf
1 changed files with 2 additions and 2 deletions
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litex/soc/interconnect/wishbone.py
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@ -199,8 +199,8 @@ class Decoder(Module):
class InterconnectShared(Module): class InterconnectShared(Module):
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): def __init__(self, masters, slaves, register=False, timeout_cycles=1e6,data_width=32):
shared = Interface() shared = Interface(data_width=data_width)
self.submodules.arbiter = Arbiter(masters, shared) self.submodules.arbiter = Arbiter(masters, shared)
self.submodules.decoder = Decoder(shared, slaves, register) self.submodules.decoder = Decoder(shared, slaves, register)
if timeout_cycles is not None: if timeout_cycles is not None: