litex/soc/interconnect/wishbone.py: add data_width param

2021-12-31 13:27:27 +08:00 · 2021-12-31 13:27:27 +08:00 · a8c8e4e3cf
parent e87e7ff31c
commit a8c8e4e3cf
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@ -199,8 +199,8 @@ class Decoder(Module):


 class InterconnectShared(Module):
-    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        shared = Interface()
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6,data_width=32):
+        shared = Interface(data_width=data_width)
        self.submodules.arbiter = Arbiter(masters, shared)
        self.submodules.decoder = Decoder(shared, slaves, register)
        if timeout_cycles is not None: