Merge branch 'master' of http://github.com/enjoy-digital/litex
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commit
a8f819fec2
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@ -243,10 +243,9 @@ class XilinxVivadoToolchain:
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if run:
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if synth_mode == "yosys":
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common._run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
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elif synth_mode == "vivado":
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_run_vivado(build_name, toolchain_path, source)
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else:
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raise OSError("Error!")
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_run_vivado(build_name, toolchain_path, source)
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os.chdir(cwd)
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