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integration/soc: add_ethernet: honor self.map["ethmac"], if present 

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2020-03-10 19:45:45 -04:00
parent 846a2720b7
commit a904034811
1 changed files with 2 additions and 1 deletions
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litex/soc/integration/soc.py
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@ -1044,7 +1044,8 @@ class LiteXSoC(SoC):
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
ethmac_region = SoCRegion(size=0x2000, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None),
size=0x2000, cached=False)
self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")