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genlib/cdc/MultiReg: output clock domain defaults to sys
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@ -23,7 +23,7 @@ class MultiRegImpl:
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return Fragment(comb, {self.odomain: o_sync})
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class MultiReg(Special):
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def __init__(self, i, o, odomain, n=2):
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def __init__(self, i, o, odomain="sys", n=2):
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Special.__init__(self)
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self.i = i
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self.o = o
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