examples/sim/fir: convert to new API

examples/sim/fir.py

@@ -9,37 +9,35 @@ from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl import verilog
 from migen.genlib.misc import optree
-from migen.fhdl import autofragment
 from migen.sim.generic import Simulator
 
 # A synthesizable FIR filter.
-class FIR:
+class FIR(Module):
 	def __init__(self, coef, wsize=16):
 		self.coef = coef
 		self.wsize = wsize
 		self.i = Signal((self.wsize, True))
 		self.o = Signal((self.wsize, True))
 	
-	def get_fragment(self):
+		###
+
 		muls = []
-		sync = []
 		src = self.i
 		for c in self.coef:
 			sreg = Signal((self.wsize, True))
-			sync.append(sreg.eq(src))
+			self.sync += sreg.eq(src)
 			src = sreg
 			c_fp = int(c*2**(self.wsize - 1))
 			muls.append(c_fp*sreg)
 		sum_full = Signal((2*self.wsize-1, True))
-		sync.append(sum_full.eq(optree("+", muls)))
-		comb = [self.o.eq(sum_full[self.wsize-1:])]
-		return Fragment(comb, sync)
+		self.sync += sum_full.eq(optree("+", muls))
+		self.comb += self.o.eq(sum_full[self.wsize-1:])
 
 # A test bench for our FIR filter.
 # Generates a sine wave at the input and records the output.
 class TB(Module):
-	def __init__(self, fir, frequency):
-		self.fir = fir
+	def __init__(self, coef, frequency):
+		self.submodules.fir = FIR(coef)
 		self.frequency = frequency
 		self.inputs = []
 		self.outputs = []
@@ -54,16 +52,14 @@ class TB(Module):
 def main():
 	# Compute filter coefficients with SciPy.
 	coef = signal.remez(30, [0, 0.1, 0.2, 0.4, 0.45, 0.5], [0, 1, 0])
-	fir = FIR(coef)
 	
 	# Simulate for different frequencies and concatenate
 	# the results.
 	in_signals = []
 	out_signals = []
 	for frequency in [0.05, 0.1, 0.25]:
-		tb = TB(fir, frequency)
-		fragment = autofragment.from_local()
-		sim = Simulator(fragment)
+		tb = TB(coef, frequency)
+		sim = Simulator(tb)
 		sim.run(200)
 		del sim
 		in_signals += tb.inputs
@@ -75,7 +71,7 @@ def main():
 	plt.show()
 	
 	# Print the Verilog source for the filter.
-	print(verilog.convert(fir.get_fragment(),
-		ios={fir.i, fir.o}))
+	fir = FIR(coef)
+	print(verilog.convert(fir, ios={fir.i, fir.o}))
 
 main()