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uart: rename wishbone to bridge

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This commit is contained in:
Florent Kermarrec 2015-05-09 16:24:28 +02:00
parent fb5397aa82
commit a99aa9c7fd
5 changed files with 4 additions and 4 deletions
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2
misoclib/com/liteeth/example_designs/targets/base.py
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@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.uart.bridge import UARTWishboneBridge
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

2
misoclib/com/litepcie/example_designs/targets/dma.py
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@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
from misoclib.soc import SoC from misoclib.soc import SoC
from misoclib.tools.litescope.common import * from misoclib.tools.litescope.common import *
from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.uart.bridge import UARTWishboneBridge
from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
from misoclib.com.litepcie.core import Endpoint from misoclib.com.litepcie.core import Endpoint

0
misoclib/com/uart/wishbone.py → misoclib/com/uart/bridge.py
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2
misoclib/mem/litesata/example_designs/targets/bist.py
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@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.uart.bridge import UARTWishboneBridge
from misoclib.mem.litesata.common import * from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy import LiteSATAPHY from misoclib.mem.litesata.phy import LiteSATAPHY

2
misoclib/tools/litescope/example_designs/targets/simple.py
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@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.tools.litescope.frontend.io import LiteScopeIO from misoclib.tools.litescope.frontend.io import LiteScopeIO
from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.com.uart.wishbone import UARTWishboneBridge from misoclib.com.uart.bridge import UARTWishboneBridge
class LiteScopeSoC(SoC, AutoCSR): class LiteScopeSoC(SoC, AutoCSR):
csr_map = { csr_map = {