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CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2023-07-20 16:30:48 +02:00
parent c00f61d9d7
commit aae15737cd
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@ -44,6 +44,7 @@
- gen/fhdl/verilog : Improved signal sort by name instead of duid to improve reproducibility. - gen/fhdl/verilog : Improved signal sort by name instead of duid to improve reproducibility.
- litedram/frontend/dma : Added last generation on end of DMA for LiteDRAMDMAReader. - litedram/frontend/dma : Added last generation on end of DMA for LiteDRAMDMAReader.
- litepcie/frontend/dma : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic. - litepcie/frontend/dma : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic.
- soc/add_uartbone/sata/sdcard : Added support for multiple instances in gateware as for the other cores.
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