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soc/add_sata: Integrate LiteSATAIdentify module.

This commit is contained in:
Florent Kermarrec 2022-05-18 15:27:13 +02:00
parent 5df1f5f511
commit aaf03b3860
1 changed files with 8 additions and 1 deletions
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9
litex/soc/integration/soc.py
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@ -1774,10 +1774,11 @@ class LiteXSoC(SoC):
self.add_constant("SDCARD_DEBUG") self.add_constant("SDCARD_DEBUG")
# Add SATA ------------------------------------------------------------------------------------- # Add SATA -------------------------------------------------------------------------------------
def add_sata(self, name="sata", phy=None, mode="read+write"): def add_sata(self, name="sata", phy=None, mode="read+write", with_identify=True):
# Imports. # Imports.
from litesata.core import LiteSATACore from litesata.core import LiteSATACore
from litesata.frontend.arbitration import LiteSATACrossbar from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.identify import LiteSATAIdentify, LiteSATAIdentifyCSR
from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA
# Checks. # Checks.
@ -1798,6 +1799,12 @@ class LiteXSoC(SoC):
self.check_if_exists("sata_crossbar") self.check_if_exists("sata_crossbar")
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Identify.
if with_identify:
sata_identify = LiteSATAIdentify(self.sata_crossbar.get_port())
self.submodules += sata_identify
self.submodules.sata_identify = LiteSATAIdentifyCSR(sata_identify)
# Sector2Mem DMA. # Sector2Mem DMA.
if "read" in mode: if "read" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width) bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)