soc/add_sata: Integrate LiteSATAIdentify module.
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@ -1774,10 +1774,11 @@ class LiteXSoC(SoC):
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self.add_constant("SDCARD_DEBUG")
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self.add_constant("SDCARD_DEBUG")
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# Add SATA -------------------------------------------------------------------------------------
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# Add SATA -------------------------------------------------------------------------------------
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def add_sata(self, name="sata", phy=None, mode="read+write"):
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def add_sata(self, name="sata", phy=None, mode="read+write", with_identify=True):
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# Imports.
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# Imports.
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from litesata.core import LiteSATACore
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from litesata.core import LiteSATACore
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from litesata.frontend.arbitration import LiteSATACrossbar
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from litesata.frontend.arbitration import LiteSATACrossbar
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from litesata.frontend.identify import LiteSATAIdentify, LiteSATAIdentifyCSR
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from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA
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from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA
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# Checks.
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# Checks.
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@ -1798,6 +1799,12 @@ class LiteXSoC(SoC):
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self.check_if_exists("sata_crossbar")
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self.check_if_exists("sata_crossbar")
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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# Identify.
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if with_identify:
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sata_identify = LiteSATAIdentify(self.sata_crossbar.get_port())
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self.submodules += sata_identify
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self.submodules.sata_identify = LiteSATAIdentifyCSR(sata_identify)
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# Sector2Mem DMA.
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# Sector2Mem DMA.
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if "read" in mode:
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if "read" in mode:
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bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
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bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
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