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Set environmental variables in python

This commit is contained in:
developandplay 2021-06-27 01:07:27 +02:00
parent e3f6d8349b
commit ac217d818f
1 changed files with 16 additions and 9 deletions
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23
litex/soc/cores/cpu/blackparrot/core.py
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@ -116,15 +116,22 @@ class BlackParrotRV64(CPU):
bp_litex = os.path.join(vdir, "bp_litex") bp_litex = os.path.join(vdir, "bp_litex")
copyfile(os.path.join(bp_litex, "cce_ucode.mem"), "/tmp/cce_ucode.mem") copyfile(os.path.join(bp_litex, "cce_ucode.mem"), "/tmp/cce_ucode.mem")
# Add Verilog sources # Set environmental variables
try: os.environ["BP"] = vdir
os.environ["BP"] os.environ["BP_LITEX_DIR"] = bp_litex
os.environ["LITEX"]
os.environ["BP_COMMON_DIR"] = os.path.join(vdir, "bp_common")
os.environ["BP_FE_DIR"] = os.path.join(vdir, "bp_fe")
os.environ["BP_BE_DIR"] = os.path.join(vdir, "bp_be")
os.environ["BP_ME_DIR"] = os.path.join(vdir, "bp_me")
os.environ["BP_TOP_DIR"] = os.path.join(vdir, "bp_top")
external = os.path.join(vdir, "external")
os.environ["BP_EXTERNAL_DIR"] = external
os.environ["BASEJUMP_STL_DIR"] = os.path.join(external, "basejump_stl")
os.environ["LITEX_FPGA_DIR"] = os.path.join(bp_litex, "fpga")
os.environ["LITEX_SIMU_DIR"] = os.path.join(bp_litex, "simulation")
self.add_sources(platform, variant) self.add_sources(platform, variant)
except:
RED = '\033[91m'
print(RED + "Please set environment variables first, refer to readme file under litex/soc/cores/cpu/blackparrot for details!")
sys.exit(1)
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):