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k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)

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Florent Kermarrec 2014-08-14 16:32:29 +02:00 committed by Sebastien Bourdeauducq
parent 2e4bfe154f
commit acbba37f5f
1 changed files with 1 additions and 0 deletions
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misoclib/sdramphy/k7ddrphy.py
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@ -185,6 +185,7 @@ class K7DDRPHY(Module):
i_CE1=1, i_CE1=1,
i_RST=ResetSignal(), i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_BITSLIP=0,
o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i], o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i],
o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i], o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i],
o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i], o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i],