soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)

Fixes: 002aad7a4 Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2024-01-01 13:32:40 -05:00 · 2024-01-01 13:32:40 -05:00 · acf07a21c9
parent 56f61986f0
commit acf07a21c9
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1651,9 +1651,9 @@ class LiteXSoC(SoC):
                    else:
                        mem_wb  = wishbone.Interface(
                            data_width = self.cpu.mem_axi.data_width,
-                            adr_width  = 32-log2_int(mem_bus.data_width//8,
+                            adr_width  = 32-log2_int(mem_bus.data_width//8),
                            addressing = "word",
-                        ))
+                        )
                        mem_a2w = axi.AXI2Wishbone(
                            axi          = mem_bus,
                            wishbone     = mem_wb,