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soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)
Fixes: 002aad7a4
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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1 changed files with 2 additions and 2 deletions
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@ -1651,9 +1651,9 @@ class LiteXSoC(SoC):
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else:
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else:
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mem_wb = wishbone.Interface(
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mem_wb = wishbone.Interface(
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data_width = self.cpu.mem_axi.data_width,
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data_width = self.cpu.mem_axi.data_width,
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adr_width = 32-log2_int(mem_bus.data_width//8,
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adr_width = 32-log2_int(mem_bus.data_width//8),
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addressing = "word",
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addressing = "word",
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))
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)
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mem_a2w = axi.AXI2Wishbone(
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mem_a2w = axi.AXI2Wishbone(
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axi = mem_bus,
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axi = mem_bus,
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wishbone = mem_wb,
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wishbone = mem_wb,
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