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soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)

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Fixes: 002aad7a4

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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gsomlo 2024-01-01 13:32:40 -05:00 committed by GitHub
parent 56f61986f0
commit acf07a21c9
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1 changed files with 2 additions and 2 deletions
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litex/soc/integration/soc.py
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@ -1651,9 +1651,9 @@ class LiteXSoC(SoC):
else: else:
mem_wb = wishbone.Interface( mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width, data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(mem_bus.data_width//8, adr_width = 32-log2_int(mem_bus.data_width//8),
addressing = "word", addressing = "word",
)) )
mem_a2w = axi.AXI2Wishbone( mem_a2w = axi.AXI2Wishbone(
axi = mem_bus, axi = mem_bus,
wishbone = mem_wb, wishbone = mem_wb,