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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.

This commit is contained in:
Florent Kermarrec 2020-03-05 11:19:29 +01:00
parent 3770195048
commit ad11ff39ad
1 changed files with 1 additions and 1 deletions
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2
litex/boards/targets/versa_ecp5.py
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@ -72,7 +72,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------