soc/cores/i2c: add interrupt

litex/soc/cores/i2c.py

@@ -11,7 +11,7 @@
 
 from migen import *
 from litex.soc.interconnect import wishbone
-
+from litex.soc.interconnect.csr_eventmanager import *
 
 # I2C-----------------------------------------------------------------------------------------------
 
@@ -237,6 +237,12 @@ class I2CMaster(Module):
             i2c.sda_i.eq(self.sda_t.i),
         ]
 
+        # Event Manager.
+        self.submodules.ev = EventManager()
+        self.ev.idle       = EventSourceLevel()
+        self.ev.finalize()
+        self.comb += self.ev.idle.trigger.eq(i2c.idle)
+
 I2C_XFER_ADDR, I2C_CONFIG_ADDR = range(2)
 (
     I2C_ACK,