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soc_sdram: Don't add the L2 Cache when there's no wishbone bus

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Florent Kermarrec 2019-09-23 15:53:07 +02:00
parent ae38fd4244
commit ad8830d977
2 changed files with 39 additions and 36 deletions
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1
litex/soc/integration/soc_core.py
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@ -232,6 +232,7 @@ class SoCCore(Module):
self.with_uart = with_uart self.with_uart = with_uart
self.uart_baudrate = uart_baudrate self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------ # Modules instances ------------------------------------------------------------------------

74
litex/soc/integration/soc_sdram.py
View file

@ -68,50 +68,52 @@ class SoCSDRAM(SoCCore):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
# LiteDRAM core ------------------------------------------------------------------------------- # LiteDRAM core ----------------------------------------------------------------------------
self.submodules.sdram = ControllerInjector( self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, self.clk_freq, **kwargs) phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
# LiteDRAM port ------------------------------------------------------------------------------- # SoC <--> L2 Cache <--> LiteDRAM ----------------------------------------------------------
port = self.sdram.crossbar.get_port() if self.with_wishbone:
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2 # LiteDRAM port ------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# Parameters ------ ------------------------------------------------------------------------ # Parameters ---------------------------------------------------------------------------
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2 l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2
# SoC <--> L2 Cache Wishbone interface ----------------------------------------------------- # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram) self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
# L2 Cache --------------------------------------------------------------------------------- # L2 Cache -----------------------------------------------------------------------------
l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
from litex.build.xilinx.vivado import XilinxVivadoToolchain from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we:
from migen.fhdl.simplify import FullMemoryWE from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache) self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else: else:
self.submodules.l2_cache = l2_cache self.submodules.l2_cache = l2_cache
self.config["L2_SIZE"] = l2_size self.config["L2_SIZE"] = l2_size
# L2 Cache <--> LiteDRAM bridge ------------------------------------------------------------ # L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
if use_axi: if use_axi:
axi_port = LiteDRAMAXIPort( axi_port = LiteDRAMAXIPort(
port.data_width, port.data_width,
port.address_width + log2_int(port.data_width//8)) port.address_width + log2_int(port.data_width//8))
axi2native = LiteDRAMAXI2Native(axi_port, port) axi2native = LiteDRAMAXI2Native(axi_port, port)
self.submodules += axi2native self.submodules += axi2native
self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port) self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port)
else: else:
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
def do_finalize(self): def do_finalize(self):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size: