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soc_sdram: Don't add the L2 Cache when there's no wishbone bus

This commit is contained in:
Florent Kermarrec 2019-09-23 15:53:07 +02:00
parent ae38fd4244
commit ad8830d977
2 changed files with 39 additions and 36 deletions
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1
litex/soc/integration/soc_core.py
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@ -232,6 +232,7 @@ class SoCCore(Module):
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------

14
litex/soc/integration/soc_sdram.py
View File

@ -68,15 +68,17 @@ class SoCSDRAM(SoCCore):
assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
# LiteDRAM core -------------------------------------------------------------------------------
# LiteDRAM core ----------------------------------------------------------------------------
self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
# LiteDRAM port -------------------------------------------------------------------------------
# SoC <--> L2 Cache <--> LiteDRAM ----------------------------------------------------------
if self.with_wishbone:
# LiteDRAM port ------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# Parameters ------ ------------------------------------------------------------------------
# Parameters ---------------------------------------------------------------------------
main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8
@ -85,12 +87,12 @@ class SoCSDRAM(SoCCore):
l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2
# SoC <--> L2 Cache Wishbone interface -----------------------------------------------------
# SoC <--> L2 Cache Wishbone interface -------------------------------------------------
wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
# L2 Cache ---------------------------------------------------------------------------------
# L2 Cache -----------------------------------------------------------------------------
l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
@ -102,7 +104,7 @@ class SoCSDRAM(SoCCore):
self.submodules.l2_cache = l2_cache
self.config["L2_SIZE"] = l2_size
# L2 Cache <--> LiteDRAM bridge ------------------------------------------------------------
# L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
if use_axi:
axi_port = LiteDRAMAXIPort(
port.data_width,