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pytholite: fix bit width of selection signal

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Sebastien Bourdeauducq 2012-11-30 17:07:32 +01:00
parent cfb23c442f
commit adb1565d7a
1 changed files with 1 additions and 1 deletions
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2
migen/pytholite/reg.py
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@ -40,7 +40,7 @@ class ImplRegister:
def finalize(self): def finalize(self):
if self.finalized: if self.finalized:
raise FinalizeError raise FinalizeError
self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name) self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
self.finalized = True self.finalized = True
def get_fragment(self): def get_fragment(self):