pytholite: fix bit width of selection signal
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@ -40,7 +40,7 @@ class ImplRegister:
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def finalize(self):
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def finalize(self):
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if self.finalized:
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if self.finalized:
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raise FinalizeError
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raise FinalizeError
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self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name)
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self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
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self.finalized = True
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self.finalized = True
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def get_fragment(self):
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def get_fragment(self):
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