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microwatt: Correct SoCRegion typo 

Fixes: 45b9636902 ("integration/soc: Avoid soc_region_cls workaround and update CPUs.")
This commit is contained in:
Joel Stanley 2023-06-18 21:55:27 +09:30
parent 6e5651b320
commit ae22f4028a
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/cpu/microwatt/core.py
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@ -154,7 +154,7 @@ class Microwatt(CPU):
int_level_in = self.interrupt, int_level_in = self.interrupt,
) )
xicsicp_region = SoCRegion(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False) xicsicp_region = SoCRegion(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False)
xicsics_region = SocRegion(origin=soc.mem_map.get("xicsics"), size=4096, cached=False) xicsics_region = SoCRegion(origin=soc.mem_map.get("xicsics"), size=4096, cached=False)
soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region) soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region) soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)